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femtoclocks? crystal-to-3.3v lvpecl frequency synthesizer ics843004-01 idt ? / ics ? 3.3v lvpecl frequency synthesizer 1 ics843004-01 rev b june 30, 2006 g eneral d escription the ics843004-01 is a 4 output lvpecl synthesizer optimized to generate ethernet reference clock frequencies and is a member of the hiperclocks tm family of high performance clock solutions from ics. using a 25mhz 18pf parallel resonant crystal, the following frequencies can be generated based on the settings of 2 frequency select pins (f_sel[1:0]): 156.25mhz, 125mhz, 62.5mhz. the ics843004-01 uses ics? 3 rd generation low phase noise vco technology and can achieve 1ps or lower typical rms phase jitter, easily meeting ethernet jitter requirements. the ics843004-01 is packaged in a small 24-pin tssop package. f eatures four 3.3v lvpecl outputs selectable crystal oscillator interface or lvcmos/lvttl single-ended input supports the following output frequencies: 156.25mhz, 125mhz and 62.5mhz vco range: 560mhz - 680mhz rms phase jitter @ 156.25mhz, using a 25mhz crystal (1.875mhz - 20mhz): 0.57ps (typical) rms phase noise at 156.25mhz (typical) phase noise: offset noise p o w er 100hz ............... -95.5 dbc/hz 1khz ................ -118 dbc/hz 10khz ................ -126 dbc/hz 100khz ......... .... -126.6 dbc/hz full 3.3v supply mode -30c to 85c ambient operating temperature available in both standard and lead-free rohs compliant packages hiperclocks? ic s p in a ssignment 11 0 1 0 phase detector vco 625mhz (w/25mhz reference) osc m = 25 (fixed) f_sel[1:0] 0 0 4 0 1 5 1 0 10 1 1 not used 2 ics843004-01 24-lead tssop 4.40mm x 7.8mm x 0.92mm package body g package top view nq1 q1 v cc o q0 nq0 mr npll_sel nc v cca f_sel0 v cc f_sel1 1 2 3 4 5 6 7 8 9 10 11 12 nq2 q2 v cco q3 nq3 v ee v cc nxtal_sel test_clk v ee xtal_in xtal_out 24 23 22 21 20 19 18 17 16 15 14 13 b lock d iagram s t u p n i y c n e u q e r f t u p t u o ) . f e r z h m 5 2 ( 1 l e s _ f0 l e s _ f r e d i v i d m e u l a v r e d i v i d n e u l a v n / m e u l a v r e d i v i d 00 5 24 5 2 . 65 2 . 6 5 1 01 5 25 5 5 2 1 10 5 20 15 . 25 . 2 6 11 5 2d e s u t o nd e s u t o n f requency s elect f unction t able f_sel[1:0] npll_sel test_clk xtal_in xtal_out nxtal_sel mr q0 nqo q1 nq1 q2 nq2 q3 nq3 pulldown pulldown 25mhz pulldown pulldown pulldown
idt ? / ics ? 3.3v lvpecl frequency synthesizer 2 ics843004-01 rev b june 30, 2006 ics843004-01 femtoclocks? crystal-to-3.3v lvpecl frequency synthesizer t able 1. p in d escriptions t able 2. p in c haracteristics r e b m u ne m a ne p y tn o i t p i r c s e d 2 , 11 q , 1 q nt u p t u o. s l e v e l e c a f r e t n i l c e p v l . r i a p t u p t u o l a i t n e r e f f i d 2 2 , 3v o c c r e w o p. s n i p y l p p u s t u p t u o 5 , 40 q n , 0 qt u p u o. s l e v e l e c a f r e t n i l c e p v l . r i a p t u p t u o l a i t n e r e f f i d 6r mt u p n in w o d l l u p e r a s r e d i v i d l a n r e t n i e h t , h g i h c i g o l n e h w . t e s e r r e t s a m h g i h e v i t c a x q n s t u p t u o d e t r e v n i e h t d n a w o l o g o t x q s t u p t u o e u r t e h t g n i s u a c t e s e r e r a s t u p t u o e h t d n a s r e d i v i d l a n r e t n i e h t , w o l c i g o l n e h w . h g i h o g o t . s l e v e l e c a f r e t n i l t t v l / s o m c v l . d e l b a n e 7l e s _ l l p nt u p n in w o d l l u p n e h w . s r e d i v i d e h t o t t u p n i s a k l c _ t s e t d n a l l p e h t n e e w t e b s t c e l e s k c o l c e c n e r e f e r e h t s t c e l e s e d , h g i h n e h w . ) e l b a n e l l p ( l l p s t c e l e s , w o l . s l e v e l e c a f r e t n i l t t v l / s o m c v l . ) s s a p y b l l p ( 8c nd e s u n u. t c e n n o c o n 9v a c c r e w o p. n i p y l p p u s g o l a n a 2 1 , 0 1 , 0 l e s _ f 1 l e s _ f t u p n in w o d l l u p. s l e v e l e c a f r e t n i l t t v l / s o m c v l . s n i p t c e l e s y c n e u q e r f 8 1 , 1 1v c c r e w o p. n i p y l p p u s e r o c 4 1 , 3 1 , t u o _ l a t x n i _ l a t x t u p n i , t u p t u o e h t s i t u o _ l a t x . e c a f r e t n i l a t s y r c t n a n o s e r l e l l a r a p . t u p n i e h t s i n i _ l a t x 9 1 , 5 1v e e r e w o p. s n i p y l p p u s e v i t a g e n 6 1k l c _ t s e tt u p n in w o d l l u p. t u p n i k c o l c l t t v l / s o m c v l 7 1l e s _ l a t x nt u p n in w o d l l u p e c n e r e f e r l l p e h t e h t s a s t u p n i k l c _ t s e t r o l a t s y r c n e e w t e b s t c e l e s . h g i h n e h w k l c _ t s e t s t c e l e s . w o l n e h w s t u p n i l a t x s t c e l e s . e c r u o s . s l e v e l e c a f r e t n i l t t v l / s o m c v l 1 2 , 0 23 q , 3 q nt u p t u o. s l e v e l e c a f r e t n i l c e p v l . r i a p t u p t u o l a i t n e r e f f i d 4 2 , 3 22 q n , 2 qt u p t u o. s l e v e l e c a f r e t n i l c e p v l . r i a p t u p t u o l a i t n e r e f f i d : e t o n n w o d l l u p . s e u l a v l a c i p y t r o f , s c i t s i r e t c a r a h c n i p , 2 e l b a t e e s . s r o t s i s e r t u p n i l a n r e t n i o t s r e f e r l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u c n i e c n a t i c a p a c t u p n i 4f p r n w o d l l u p r o t s i s e r n w o d l l u p t u p n i 1 5k ?
idt ? / ics ? 3.3v lvpecl frequency synthesizer 3 ics843004-01 rev b june 30, 2006 ics843004-01 femtoclocks? crystal-to-3.3v lvpecl frequency synthesizer t able 3a. p ower s upply dc c haracteristics , v cc = v cca = v cco = 3.3v5%, t a = -30c to 85c t able 3b. lvcmos / lvttl dc c haracteristics , v cc = v cca = v cco = 3.3v5%, t a = -30c to 85c l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u v h i e g a t l o v h g i h t u p n i 2v c c 3 . 0 +v v l i t u p n i e g a t l o v w o l , l e s _ l a t x n , l e s _ l l p n r m , 1 l e s _ f , 0 l e s _ f 3 . 0 -8 . 0v k l c _ t s e t3 . 0 -3 . 1v i h i t u p n i t n e r r u c h g i h , r m , k l c _ t s e t , l e s _ l a t x n , l e s _ l l p n 1 l e s _ f , 0 l e s _ f v c c v = n i v 5 6 4 . 3 =0 5 1a i l i t u p n i t n e r r u c w o l , r m , k l c _ t s e t , l e s _ l a t x n , l e s _ l l p n 1 l e s _ f , 0 l e s _ f v c c v , v 5 6 4 . 3 = n i v 0 =5 -a a bsolute m aximum r atings supply voltage, v cc 4.6v inputs, v i -0.5v to v cc + 0.5v outputs, i o contin uous current 50ma surge current 100ma package thermal impedance, ja 70c/w (0 mps) storage temperature, t stg -65c to 150c note: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only. func- tional operation of product at these conditions or any condi- tions beyond those listed in the dc characteristics or ac characteristics is not implied. exposure to absolute maxi- mum rating conditions for extended periods may affect prod- uct reliability. l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u v c c e g a t l o v y l p p u s e r o c 5 3 1 . 33 . 35 6 4 . 3v v a c c e g a t l o v y l p p u s g o l a n a 5 3 1 . 33 . 35 6 4 . 3v v o c c e g a t l o v y l p p u s t u p t u o 5 3 1 . 33 . 35 6 4 . 3v i e e t n e r r u c y l p p u s r e w o p 5 3 1a m i a c c t n e r r u c y l p p u s g o l a n ai n i d e d u l c n i e e 5 1a m t able 3c. lvpecl dc c haracteristics , v cc = v cca = v cco = 3.3v5%, t a = -30c to 85c l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u v h o 1 e t o n ; e g a t l o v h g i h t u p t u ov o c c 4 . 1 -v o c c 9 . 0 -v v l o 1 e t o n ; e g a t l o v w o l t u p t u ov o c c 0 . 2 -v o c c 7 . 1 -v v g n i w s g n i w s e g a t l o v t u p t u o k a e p - o t - k a e p 6 . 00 . 1v 0 5 h t i w d e t a n i m r e t s t u p t u o : 1 e t o n ? v o t o c c . v 2 -
idt ? / ics ? 3.3v lvpecl frequency synthesizer 4 ics843004-01 rev b june 30, 2006 ics843004-01 femtoclocks? crystal-to-3.3v lvpecl frequency synthesizer t able 5. ac c haracteristics , v cc = v cca = v cco = 3.3v5%, t a = -30c to 85c t able 4. c rystal c haracteristics r e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u n o i t a l l i c s o f o e d o m l a t n e m a d n u f y c n e u q e r f 5 2z h m ) r s e ( e c n a t s i s e r s e i r e s t n e l a v i u q e 0 5 ? e c n a t i c a p a c t n u h s 7f p . l a t s y r c t n a n o s e r l e l l a r a p f p 8 1 n a g n i s u d e z i r e t c a r a h c : e t o n l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u f t u o y c n e u q e r f t u p t u o 0 0 = ] 0 : 1 [ l e s _ f0 4 10 7 1z h m 1 0 = ] 0 : 1 [ l e s _ f2 1 16 3 1z h m 0 1 = ] 0 : 1 [ l e s _ f6 58 6z h m t ) o ( k s2 , 1 e t o n ; w e k s t u p t u o 0 3s p t ) ? ( t i j3 e t o n ; r e t t i j e s a h p s m r ) z h m 0 2 - z h m 5 7 8 . 1 ( z h m 5 2 . 6 5 17 5 . 0s p ) z h m 0 2 - z h m 5 7 8 . 1 ( z h m 5 2 13 6 . 0s p ) z h m 0 2 - z h m 5 7 8 . 1 ( z h m 5 . 2 61 8 . 0s p t r t / f e m i t l l a f / e s i r t u p t u o% 0 8 o t % 0 20 0 30 0 6s p c d oe l c y c y t u d t u p t u o 9 41 5% . s n o i t i d n o c d a o l l a u q e h t i w d n a s e g a t l o v y l p p u s e m a s e h t t a s t u p t u o n e e w t e b w e k s s a d e n i f e d : 1 e t o n v t a d e r u s a e m o c c . 2 / . 5 6 d r a d n a t s c e d e j h t i w e c n a d r o c c a n i d e n i f e d s i r e t e m a r a p s i h t : 2 e t o n . d e s u e c r u o s t u p n i e h t n o t n e d n e p e d s i r e t t i j e s a h p : 3 e t o n
idt ? / ics ? 3.3v lvpecl frequency synthesizer 5 ics843004-01 rev b june 30, 2006 ics843004-01 femtoclocks? crystal-to-3.3v lvpecl frequency synthesizer 125mhz rms phase jitter (random) 1.875mhz to 20mhz = 0.63ps (typical) o ffset f requency (h z ) n oise p ower dbc hz 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 -190 100 1k 10k 100k 1m 10m 100m t ypical p hase n oise at 125mh z t ypical p hase n oise at 62.5mh z 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 -190 62.5mhz rms phase jitter (random) 1.875mhz to 20mhz = 0.81ps (typical) o ffset f requency (h z ) n oise p ower dbc hz raw phase noise data ? 100 1k 10k 100k 1m 10m 100m phase noise result by adding 10gb ethernet filter to raw data 10gb ethernet filter ? ? phase noise result by adding 10gb ethernet filter to raw data 10gb ethernet filter ? ? raw phase noise data ?
idt ? / ics ? 3.3v lvpecl frequency synthesizer 6 ics843004-01 rev b june 30, 2006 ics843004-01 femtoclocks? crystal-to-3.3v lvpecl frequency synthesizer 100 1k 10k 100k 1m 10m 100m t ypical p hase n oise at 156.25mh z 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 -190 156.25mhz rms phase jitter (random) 1.875mhz to 20mhz = 0.57ps (typical) o ffset f requency (h z ) n oise p ower dbc hz phase noise result by adding 10gb ethernet filter to raw data raw phase noise data 10gb ethernet filter ? ? ?
idt ? / ics ? 3.3v lvpecl frequency synthesizer 7 ics843004-01 rev b june 30, 2006 ics843004-01 femtoclocks? crystal-to-3.3v lvpecl frequency synthesizer p arameter m easurement i nformation t pw t period t pw t period odc = x 100% q0:q3 rms p hase j itter o utput s kew 3.3v c ore /3.3v o utput l oad ac t est c ircuit scope qx nqx lvpecl 2v -1.3v0.165v o utput r ise /f all t ime clock outputs 20% 80% 80% 20% t r t f v sw i n g v cc , v cca , v cco v ee nq0:nq3 o utput d uty c ycle /p ulse w idth /p eriod t sk(o) qy qx nqy nqx phase noise mas k offset frequency f 1 f 2 phase noise plot rms jitter = area under the masked phase noise plot noise power
idt ? / ics ? 3.3v lvpecl frequency synthesizer 8 ics843004-01 rev b june 30, 2006 ics843004-01 femtoclocks? crystal-to-3.3v lvpecl frequency synthesizer c rystal i nput i nterface the ics843004-01 has been characterized with 18pf parallel resonant crystals. the capacitor values shown in figure 2 below figure 2. c rystal i npu t i nterface were determined using a 25mhz, 18pf parallel resonant crystal and were chosen to minimize the ppm error. a pplication i nformation as in any high speed analog circuitry, the power supply pins are vulnerable to random noise. the ics843004-01 provides separate power supplies to isolate any high switching noise from the outputs to the internal pll. v cc , v cca , and v cco should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. to achieve optimum jitter performance, power supply isolation is required. figure 1 illustrates how a 10 ? resistor along with a 10f and a .01 f bypass capacitor should be connected to each v cca . p ower s upply f iltering t echniques f igure 1. p ower s upply f iltering 10 ? v cca 10 f .01 f 3.3v .01 f v cc c1 33p x1 18pf parallel crystal c2 27p xtal_out xtal_in i nputs : c rystal i nput : for applications not requiring the use of the crystal oscillator input, both xtal_in and xtal_out can be left floating. though not required, but for additional protection, a 1kw resistor can be tied from xtal_in to ground. test_clk i nput : for applications not requiring the use of the test clock, it can be left floating. though not required, but for additional protection, a 1k ? resistor can be tied from the test_clk to ground. lvcmos c ontrol p ins : all control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. a 1k ? resistor can be used. r ecommendations for u nused i nput and o utput p ins o utputs : lvpecl o utput all unused lvpecl outputs can be left floating. we recommend that there is no trace attached. both sides of the differential output pair should either be left floating or terminated.
idt ? / ics ? 3.3v lvpecl frequency synthesizer 9 ics843004-01 rev b june 30, 2006 ics843004-01 femtoclocks? crystal-to-3.3v lvpecl frequency synthesizer lvcmos to xtal i nterface the xtal_in input can accept a single-ended lvcmos signal through an ac coupling capacitor. a general interface diagram is shown in figure x. the xtal_out pin can be left floating. the input edge rate can be as slow as 10ns. for lvcmos inputs, it is recommended that the amplitude be reduced from full swing to half swing in order to prevent signal interference with the power rail and to reduce noise. this configuration requires that the output f igure 3. g eneral d iagram for lvcmos d river to xtal i nput i nterface impedance of the driver (ro) plus the series resistance (rs) equals the transmission line impedance. in addition, matched termination at the crystal input will attenuate the signal in half. this can be done in one of two ways. first, r1 and r2 in parallel should equal the transmission line impedance. for most 50 ? applications, r1 and r2 can be 100 ? . this can also be accomplished by removing r1 and making r2 50 ? . r2 zo = 50 vdd ro zo = ro + rs r1 vdd xta l _ i n xta l _ o u t .1uf rs t ermination for 3.3v lvpecl o utput v cc - 2v 50 ? 50 ? rtt z o = 50 ? z o = 50 ? fout fin rtt = z o 1 ((v oh + v ol ) / (v cc ? 2)) ? 2 3.3v 125 ? 125 ? 84 ? 84 ? z o = 50 ? z o = 50 ? fout fin the clock layout topology shown below is a typical termi- nation for lvpecl outputs. the two different layouts men- tioned are recommended only as guidelines. fout and nfout are low impedance follower outputs that generate ecl/lvpecl compatible outputs. therefore, ter- minating resistors (dc current path to ground) or current sources must be used for functionality. these outputs are f igure 4b. lvpecl o utput t ermination f igure 4a. lvpecl o utput t ermination designed to drive 50 ? transmission lines. matched imped- ance techniques should be used to maximize operating fre- quency and minimize signal distortion. figures 4a and 4b show two different layouts which are recommended only as guidelines. other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations.
idt ? / ics ? 3.3v lvpecl frequency synthesizer 10 ics843004-01 rev b june 30, 2006 ics843004-01 femtoclocks? crystal-to-3.3v lvpecl frequency synthesizer vcc=3.3v vdd vcc zo = 50 ohm + - 18pf vcco r5 133 rd1 not install to logic input pins vcc zo = 50 ohm ru2 not install 3.3v r9 133 u1 ics843004-01 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 nq1 q1 vcco q0 nq0 mr npll_sel nc vcca f_sel0 vcc f_sel1 xtal_out xtal_in vee test_clk nxtal_sel vcc vee nq3 q3 vcco q2 nq2 vcc c3 10uf + - r3 133 c7 0.1u x1 25mhz zo = 50 ohm r7 133 3.3v vdd r6 82.5 vcca c4 0.01u c8 0.1u v cco=3.3v logic control input examples c6 0.1u c2 33pf c9 0.1u r2 10 ru1 1k r4 82.5 set logic input to '1' c1 27pf to logic input pins r10 82.5 zo = 50 ohm r8 82.5 set logic input to '0' vcco rd2 1k l ayout g uideline figure 5 shows a schematic example of the ics843004-01. an example of lvepcl termination is shown in this schematic. additional lvpecl termination approaches are shown in the lvpecl termination application note. in this example, an 18pf f igure 5. ics843004-01 s chematic e xample parallel resonant 25mhz crystal is used. the c1=27pf and c2=33pf are recommended for frequency accuracy. for different board layout, the c1 and c2 may be slightly adjusted for optimizing frequency accuracy.
idt ? / ics ? 3.3v lvpecl frequency synthesizer 11 ics843004-01 rev b june 30, 2006 ics843004-01 femtoclocks? crystal-to-3.3v lvpecl frequency synthesizer p ower c onsiderations this section provides information on power dissipation and junction temperature for the ics843004-01. equations and example calculations are also provided. 1. power dissipation. the total power dissipation for the ics843004-01 is the sum of the core power plus the power dissipated in the load(s). the following is the power dissipation for v cc = 3.3v + 5% = 3.465v, which gives worst case results. note: please refer to section 3 for details on calculating power dissipated in the load. ? power (core) max = v cc_max * i ee_max = 3.465v * 135ma = 467.8mw ? power (outputs) max = 30mw/loaded output pair if all outputs are loaded, the total power is 4 * 30mw = 120mw total power _max (3.465v, with all outputs switching) = 467.8mw + 120mw = 587.8mw 2. junction temperature. junction temperature, tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. the maximum recommended junction temperature for hiperclocks tm devices is 125c. the equation for tj is as follows: tj = ja * pd_total + t a tj = junction temperature ja = junction-to-ambient thermal resistance pd_total = total device power dissipation (example calculation is in section 1 above) t a = ambient temperature in order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance ja must be used. assuming a moderate air flow of 1 meter per second and a multi-layer board, the appropriate value is 65c/w per table 6 below. therefore, tj for an ambient temperature of 85c with all outputs switching is: 85c + 0.588w * 65c/w = 123.2c. this is below the limit of 125c. this calculation is only an example. tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow , and the type of board (single layer or multi-layer). t able 6. t hermal r esistance ja for 24- pin tssop, f orced c onvection ja by velocity (meters per second) 0 1 2.5 multi-layer pcb, jedec standard test boards 70c/w 65c/w 62c/w
idt ? / ics ? 3.3v lvpecl frequency synthesizer 12 ics843004-01 rev b june 30, 2006 ics843004-01 femtoclocks? crystal-to-3.3v lvpecl frequency synthesizer 3. calculations and equations. the purpose of this section is to derive the power dissipated into the load. lvpecl output driver circuit and termination are shown in figure 6. t o calculate worst case power dissipation into the load, use the following equations which assume a 50 ? load, and a termination voltage of v cc - 2v. for logic high, v out = v oh_max = v cc_max ? 0.9v (v cco_max - v oh_max ) = 0.9v for logic low, v out = v ol_max = v cc_max ? 1.7v (v cco_max - v ol_max ) = 1.7v pd_h is power dissipation when the output drives high. pd_l is the power dissipation when the output drives low. pd_h = [(v oh_max ? (v cc_max - 2v))/r l ] * (v cc_max - v oh_max ) = [(2v - (v cc _max - v oh_max )) /r l ] * (v cc_max - v oh_max ) = [(2v - 0.9v)/50 ? ] * 0.9v = 19.8mw pd_l = [(v ol_max ? (v cc_max - 2v))/r l ] * (v cc_max - v ol_max ) = [(2v - (v cc _max - v ol_max )) /r l ] * (v cc_max - v ol_max ) = [(2v - 1.7v)/50 ? ] * 1.7v = 10.2mw total power dissipation per output pair = pd_h + pd_l = 30mw f igure 6. lvpecl d river c ircuit and t ermination q1 v out v cc rl 50 v cc - 2v
idt ? / ics ? 3.3v lvpecl frequency synthesizer 13 ics843004-01 rev b june 30, 2006 ics843004-01 femtoclocks? crystal-to-3.3v lvpecl frequency synthesizer r eliability i nformation t ransistor c ount the transistor count for ics843004-01 is: 3183 t able 7. ja vs . a ir f low t able for 24 l ead tssop ja by velocity (meters per second) 0 1 2.5 multi-layer pcb, jedec standard test boards 70c/w 65c/w 62c/w
idt ? / ics ? 3.3v lvpecl frequency synthesizer 14 ics843004-01 rev b june 30, 2006 ics843004-01 femtoclocks? crystal-to-3.3v lvpecl frequency synthesizer p ackage o utline - g s uffix for 24 l ead tssop t able 8. p ackage d imensions reference document: jedec publication 95, mo-153 l o b m y s s r e t e m i l l i m m u m i n i mm u m i x a m n4 2 a- -0 2 . 1 1 a5 0 . 05 1 . 0 2 a0 8 . 05 0 . 1 b9 1 . 00 3 . 0 c9 0 . 00 2 . 0 d0 7 . 70 9 . 7 ec i s a b 0 4 . 6 1 e0 3 . 40 5 . 4 ec i s a b 5 6 . 0 l5 4 . 05 7 . 0 0 8 a a a- -0 1 . 0
idt ? / ics ? 3.3v lvpecl frequency synthesizer 15 ics843004-01 rev b june 30, 2006 ics843004-01 femtoclocks? crystal-to-3.3v lvpecl frequency synthesizer the ics logo is a registered trademark, and hiperclocks and f emto c locks are trademarks of integrated circuit systems, inc. all other trademarks are the property of their respective owners and may be registered in certain jurisdictions. t able 9. o rdering i nformation while the information presented herein has been checked for both accuracy and reliability, integrated circuit systems, incorpor ated (ics) assumes no responsibility for either its use or for infringe- ment of any patents or other rights of third parties, which would result from its use. no other circuits, patents, or licenses are implied. this product is intended for use in normal commercial and industrial applications. any other applications such as those requiring high reliability or other extraordinary environmental r equirements are not recommended without additional processing by ics. ics reserves the right to change any circuitry or specifications without notice. ics does not authorize or warrant any ics prod uct for use in life support devices or critical medical instruments. r e b m u n r e d r o / t r a pg n i k r a me g a k c a pg n i g a k c a p g n i p p i h se r u t a r e p m e t 1 0 - g a 4 0 0 3 4 8 s c i1 0 a 4 0 0 3 4 8 s c ip o s s t d a e l 4 2e b u tc 5 8 o t c 0 3 - t 1 0 - g a 4 0 0 3 4 8 s c i1 0 a 4 0 0 3 4 8 s c ip o s s t d a e l 4 2l e e r & e p a t 0 0 5 2c 5 8 o t c 0 3 - f l 1 0 - g a 4 0 0 3 4 8 s c il 1 0 a 4 0 0 3 4 s c ip o s s t " e e r f - d a e l " d a e l 4 2e b u tc 5 8 o t c 0 3 - t f l 1 0 - g a 4 0 0 3 4 8 s c il 1 0 a 4 0 0 3 4 s c ip o s s t " e e r f - d a e l " d a e l 4 2l e e r & e p a t 0 0 5 2c 5 8 o t c 0 3 - . t n a i l p m o c s h o r e r a d n a n o i t a r u g i f n o c e e r f - b p e h t e r a r e b m u n t r a p e h t o t x i f f u s " f l " n a h t i w d e r e d r o e r a t a h t s t r a p : e t o n
idt ? / ics ? 3.3v lvpecl frequency synthesizer 16 ics843004-01 rev b june 30, 2006 ics843004-01 femtoclocks? crystal-to-3.3v lvpecl frequency synthesizer t e e h s y r o t s i h n o i s i v e r v e re l b a te g a pe g n a h c f o n o i t p i r c s e de t a d b5 t4 . w o r y a l e d n o i t a g a p o r p d e t e l e d - e l b a t s c i t s i r e t c a r a h c c a 5 0 / 6 / 5 b 9 t 1 9 5 1 . t e l l u b e e r f - d a e l d e d d a - n o i t c e s s e r u t a e f - d e d d a t u p n i d e s u n u r o f s n o i t a d n e m m o c e r d n a e c a f r e t n i l a t x o t s o m c v l s n i p t u p t u o d n a . s n o i t c e s . e t o n d n a g n i k r a m , r e b m u n t r a p e e r f - d a e l d e d d a - e l b a t n o i t a m r o f n i g n i r e d r o 6 0 / 0 3 / 6
innovate with idt and accelerate your future networks. contact: www.idt.com for sales 800-345-7015 408-284-8200 fax: 408-284-2775 for tech support netcom@idt.com 480-763-2056 corporate headquarters integrated device t echnology, inc. 6024 silver creek valley road san jose, ca 95138 united states 800 345 7015 +408 284 8200 (outside u.s.) asia pacific and japan integrated device technology singapore (1997) pte. ltd. reg. no. 199707558g 435 orchard road #20-03 wisma atria singapore 238877 +65 6 887 5505 europe idt europe, limited 321 kingston road leatherhead, surrey kt22 7tu england +44 (0) 1372 363 339 fax: +44 (0) 1372 378851 ? 2006 integrated device technology, inc. all rights reserved. product specifications subject to change without notice. idt and the idt logo are trademarks of integrated device technology, inc. accelerated thinking is a service mark of integrated device technology, inc. all other brands, product names a nd marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. printed in usa ics843004-01 femtoclocks? crystal-to-3.3v lvpecl frequency synthesizer

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